1. Field of the Invention
The present invention relates to a solid-state imaging device (image sensor) used for a video camera, a digital still camera and the like, and a method of manufacturing the solid state imaging device.
2. Description of the Related Art
A solid-state imaging device (image sensor) is a semiconductor device including a plurality of pixels that are photoelectric converters and a MOS transistor that selectively reads out a signal of the pixel to read out a signal of a pixel and is used for a video camera, a digital still camera and the like, for example.
Among solid-state imaging devices, particularly what is called a CMOS-type solid-state imaging device (CMOS image sensor) manufactured in a CMOS (complementary type MOS) process has advantages of low voltage and low power consumption, multifunction, and an SOC (system on chip) in which a peripheral circuit is integrated to be a single chip.
Accordingly, a CMOS-type solid-state imaging device has attracted attention as an imaging device used in a camera for a mobile phone unit, a digital still camera and a digital video camera.
FIG. 1 is a schematic constitutional diagram (circuit configuration diagram) showing an example of a structure of a CMOS-type solid-state imaging device (CMOS image sensor).
The CMOS image sensor shown in FIG. 1 includes on the same semiconductor substrate a pixel formation region 4 in which pixels 1 each of which is made of a plurality of photodiodes 2 performing photoelectric conversion and a MOS transistor 3 selectively reading out from the photodiode 2 are arranged two-dimensionally, and peripheral circuits 5 and 6 to select a pixel and to output a signal.
Hereinafter, a region other than the pixel formation region 4, specifically a region including the pixel selecting circuit 5 and the output circuit 6 is called “peripheral circuit formation region”.
In the pixel formation region 4, each pixel 1 includes the photodiode 2 and three MOS transistors that are a transfer transistor 3, a reset transistor 7 and an amplifier transistor 8. In addition, in the peripheral circuit formation region, CMOS transistors are used to form the pixel selecting circuit 5 and the output circuit 6.
In a CMOS image sensor in related art, each circuit in a peripheral circuit formation region is formed of a CMOS transistor.
On the other hand, all of MOS transistors constituting each pixel in a pixel formation region are NMOS transistors.
The NMOS transistor constituting a pixel is made to have the same element isolation structure as an NMOS transistor normally used in a peripheral circuit formation region (for example, refer to Patent Reference 1).
FIG. 2 is a sectional view showing an element isolation structure used for a peripheral circuit formation region in a CMOS image sensor of related art.
An N-type semiconductor well region 52 and a P-type semiconductor well region 53 are formed in a semiconductor substrate 51. A PMOS transistor 54 is formed in the N-type semiconductor well region 52 and an NMOS transistor 55 is formed in the P-type semiconductor well region 53, respectively.
Further, these transistors 54 and 55 are electrically separated from each other by an element isolation portion 56 made of what is called STI (Shallow Trench Isolation) in which an element isolation layer is buried in a trench formed in the semiconductor substrate 51. In this element isolation portion 56, an oxide film is buried as the element isolation layer, for example.
Furthermore, in the CMOS image sensor of related art, since the NMOS transistor constituting a pixel is separated by the element isolation portion 56 having the same structure as the NMOS transistor used in the peripheral circuit formation region, the element isolation portion 56 in which the element isolation layer is buried in the semiconductor substrate 51 shown in FIG. 2 is similarly formed, so that adjacent pixel cells 1 are also separated in the pixel formation region 4 of FIG. 1.
In addition, source/drain diffusion layers of transistors such as the transfer transistor 3, the amplifier transistor 8, the reset transistor 7 and the like, for example, formed in each pixel cell 1 of the pixel formation region 4 are also separated by the element isolation portions 56 of a similar structure, respectively.
[Patent Reference 1] Published Japanese Patent Application No. 2003-142674 (FIG. 9)
However, in the CMOS sensor of related art, since the element isolation portion 56 is formed by burying the element isolation layer in the trench formed in the semiconductor substrate 51 as described above, there is such a case that a warp and a crystalline defect occur in the semiconductor substrate 51 due to a damage caused when forming the trench in the semiconductor substrate 51 and further due to a stress and the like caused by a difference in thermal expansion coefficient between the semiconductor substrate 51 and the buried insulation layer (element isolation layer) 56 in a heat treatment process during manufacturing.
An unnecessary electric charge (such as leakage current and dark current) is generated by the warp and crystalline defect and enters the photodiode 2.
Since the electric charge accumulated in the photodiode 2 is transferred through the transfer transistor 3, the electric charge generated by the warp and the crystal defect directly becomes a noise signal to a pixel signal.
Furthermore, when a trench is formed in a monocrystalline substrate such as a silicon substrate, a monocrystalline end portion is formed not only on the surface of the substrate but also on a sidewall of the trench and thereby an interfacial level formed in the end portion also becomes a factor of a noise signal to an image signal.
In addition, in the past, an NMOS transistor constituting a pixel has been separated by an element isolation portion 56 having the same structure as an NMOS transistor used in a peripheral circuit formation region; on the contrary, with respect to a CMOS transistor used in the peripheral circuit formation region, usually the most advanced process of miniaturization technology is applied, and further a power supply voltage is made low in terms of higher-speed operation, low power consumption, and space saving in design.
Hence, when the element isolation portion 56 is optimized corresponding to the design of the CMOS transistor in the peripheral circuit formation region, there may occur such a case that the above-described unnecessary electric charge is likely to be generated in the element isolation portion 56 in the pixel formation region 4.
The present invention addresses the above-identified, and other problems associated with conventional methods and apparatuses and provides a solid-state imaging device in which a noise to an image signal can be restrained and miniaturization can be facilitated in a peripheral circuit formation region, and a method of manufacturing the same.